Flash EEPROM memory devices comprise the largest class of electrically alterable, nonvolatile semiconductor memories. They also represent the fastest growing segment of semiconductor memories, offering high integration densities and fast read access times. Flash EEPROM devices are electrically written and erased, and allow for effectively permanent data storage. Typical flash EEPROM memories offer the ability to erase all memory cells in the device simultaneously, or to erase of selected groups of the memory cells simultaneously.
Flash devices operate by storing electrical charge on a floating gate structure. This stored charge modulates the conductance of a metal-oxide semiconductor (MOS) transistor channel underneath it. The floating gate is electrically insulated from its surroundings by a high quality dielectric, such as SiO2. A control gate that is capacitively coupled to the floating gate is used to modulate the electrical potential of the floating gate. The floating gate is formed from a conductive material such as polycrystalline silicon, which allows injected (stored) charge to be distributed over substantially the whole area of the conductive floating gate.
Alternatively a non-conductive material, such as nitride, can be used to store charge. Charge introduced into the non-conductive gate will, to a large extent, be confined to the place of introduction and, as a result, only a limited amount of charge is needed to program the memory cell. For example, PCT Patent Application WO 99/07000 discloses a two-bit non-volatile EEPROM cell using a nitride layer sandwiched in between top and bottom oxide layers. This memory cell is programmed using conventional channel-hot-electron-injection to inject electrons through the oxide and onto the nitride layer. Channel-hot-electron-injection requires the junction to overlap the nitride layer as the injection of the hot carriers occurs at the position of the maximum electrical field, which corresponds to the metallurgical junction between the drain and the well. Hence a sharp and well-controlled doping profile must be realized for such devices.
The symmetrical layout of the device allows, by appropriately selecting the voltages, electrons to be injected on either side of the non-conductive floating gate. Two bits of data can hence be stored, each bit on an opposite side of the floating gate. Erasing of the cell is done by removing the trapped electrons, through the top and/or the bottom electrode, using Fowler-Nordheim (FN) tunneling. The stored bits are read in “reverse direction.” For example, the bit at the drain side is read (e.g., the shift in threshold voltage at this point, is measured) by grounding the drain and biasing the source and the gate voltage such that saturation is reached in the channel near the source. This saturation region will mask the influence of the charge, which is stored near the source. In the ideal case only the influence of the charge stored near the drain on the cell current is measured when reading the drain bit. Thus, the doping profile must not only be engineered to enable localized injection of carriers, but also to allow screening (preventing interference) of one bit when sensing the bit on the opposite side of such a two-bit cell.
For applications where flash memory is to be integrated with high performance logic circuitry, it is desirable that the voltages required for programming, reading or erasing the memory cells are compatible with the supply voltage of the logic circuitry the flash memory is integrated with. Otherwise, complex and area consuming charge pump circuits and high voltage circuits, which are, for example, used in the decoder circuitry, must be provided on chip to provide the internal or on-chip voltages needed to operate the flash memory. The scaling of transistor dimensions towards 0.35 micrometer and below will, however, result in a corresponding scaling down of the available supply voltage from 5V towards 3.3V and below. Thus, providing sufficient power to operate current flash memory cells becomes even more difficult when the supply voltage is scaled and the memory array density is increased, leaving less area for the column drivers. Furthermore the charge pump circuits, which generate, from the scaled supply voltage, the high operating voltages for programming and erasing, become less efficient and more area consuming as the supply voltage is decreased.
Using conventional channel-hot-electron-injection (CHE) requires a gate voltage of 8–9V or above. Such programming voltages are much higher than the supply voltages employed with submicron CMOS technologies. Some programming methods have been developed to reduce the required programming voltages. For example, S. Mahapatra, S. Shukuri and J. Bude et al disclose in “Chisel Flash EEPROM-Part1: Performance and scaling”, IEEE Trans. Electron Devices, July 2002, pp. 1296–1301, a low-voltage programming technique using substrate-enhanced-hot-electron injection, also often referred to as CHISEL, to scale the gate voltage of a stacked gate memory cell down to 5–6V. The proposed device still requires higher programming voltages to attract electrical carriers towards the polysilicon floating gate, e.g. 8V at the control gate.
In European Patent Application EP 1,096,572, another low-voltage programming technique is disclosed. The approached described in this application employs the mechanism of drain-induced-secondary-impact-ionization for injecting hot electrons into the floating gate of a split-gate memory cell. Due to overlap of the floating gate over the drain junction, the drain voltage is capacitively coupled to the floating gate and assists in attracting the secondary electrons towards the floating gate. Such an approach, however, requires complicated drain engineering to produce such devices.
Although methods exist that somewhat lower the programming voltages employed, reduction of erase voltages is still troublesome. In this respect, using FN tunneling for erasing floating gate memory devices (as is common) requires the use of large electrical fields, as the dielectric layers electrically insulating the floating gate cannot be scaled (e.g., due to reliability concerns) to such an extent that the corresponding voltages are considerably lowered. Even when a negative voltage is applied to the gate, the voltages used during the step of erasing the memory cell are still above 6V due of the poor scalability of the top and bottom oxide layers through which the stored electrons must tunnel. Reliability concerns, such as moving bits (e.g., memory cells that do not retain stored charge) and stress induced leakage currents are typically considered when determining appropriate program and erase voltages.